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1 description the MT9122 voice echo canceller implements a cost effective solution for telephony voice-band echo cancellation conforming to itu-t g.165 requirements. the MT9122 architecture contains two echo cancellers which can be configured to provide dual channel 64 millisecond echo cancellation or single channel 128 millisecond echo cancellation. the MT9122 supports itu-t g.165 or g.164 tone disable requirements. the MT9122 operates in two major modes: controller or controllerless. controller mode allows access to an array of features for customizing the MT9122 operation. controllerless mode is for applications where default register settings are sufficient. features ? dual channel 64ms or single channel 128ms echo cancellation ? conforms to itu-t g.165 requirements ? itu-t g.165/g.164 disable tone detection supported on all audio paths ? narrow-band signal detection ? programmable double-talk detection threshold ? non-linear processor with adaptive suppression threshold and comfort noise insertion ? offset nulling of all pcm channels ? controllerless mode or controller mode with serial interface ? st-bus or variable-rate ssi pcm interfaces ? selectable /a-law itu-t g.711; /a-law sign mag; linear 2?s complement ? per channel selectable 12 db attenuator ? transparent data transfer and mute option ? 19.2 mhz master clock operation applications ? wireless telephony ? trunk echo cancellers figure 1 - functional block diagram linear/ /a-law + non-linear processor offset null linear/ /a-law linear/ /a-law microprocessor interface double-talk detector disable tone detector adaptive filter control narrow-band detector linear/ /a-law offset null 12db attenuator echo canceller a echo canceller b vdd vss pwrdn ic f0od f0i bclk/c4i mclk sout rin ena1 enb1 config1 config2 s1/data1 s2/data2 s3/cs s4/sclk sin rout ena2 enb2 nlp rev law format td1 td2 - programmable bypass disable tone detector issue 5 september 1996 ordering information MT9122ap 28 pin plcc MT9122ae 28 pin pdip -40 c to + 85 c MT9122 dual voice echo canceller with tone detection data sheet
2 MT9122 data sheet figure 2 - pin connections pin description pin # name description 1 ena1 ssi enable strobe / st-bus mode for rin/sout (input) . this pin has dual functions depending on whether ssi or st-bus is selected. for ssi, this strobe must be present for frame synchronization. this is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial pcm data transfer for echo canceller a on rin/sout pins. strobe period is 125 microseconds. for st-bus, this pin, in conjunction with the enb1 pin, will select the proper st-bus mode for rin/sout pins (see st-bus operation description). the selected mode applies to both echo canceller a and b. 2 enb1 ssi enable strobe / st-bus mode for rin/sout (input) .this pin has dual functions depending on whether ssi or st-bus is selected. for ssi, this is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial pcm data transfer for echo canceller b on rin/sout pins. strobe period is 125 microseconds. for st-bus, this pin, in conjunction with the ena1 pin, will select the proper st-bus mode for rin/sout pins (see st-bus operation description). the selected mode applies to both echo canceller a and b. 3 ena2 ssi enable strobe / st-bus mode for sin/rout (input) .this pin has dual functions depending on whether ssi or st-bus is selected. for ssi, this is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial pcm data transfer for echo canceller a on sin/rout pins. strobe period is 125 microseconds. for st-bus, this pin, in conjunction with the enb2 pin, will select the proper st-bus mode for sin/rout pins (see st-bus operation description). the selected mode applies to both echo canceller a and b. 4 enb2 ssi enable strobe / st-bus mode for sin/rout (input) .this pin has dual functions depending on whether ssi or st-bus is selected. for ssi, this is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial pcm data transfer for echo canceller b on sin/rout pins. strobe period is 125 microseconds. for st-bus, this pin, in conjunction with the ena2 pin, will select the proper st-bus mode for sin/rout pins (see st-bus operation description). the selected mode applies to both echo canceller a and b. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 28 27 26 25 24 23 22 21 s2/data2 vdd f0od ic td1 s1/data1 s4/sclk sout rout bclk/c4i config1 config2 sin rin nlp vss enb2 enb1 f0i format rev law ena1 pwrdn td2 ena2 mclk s3/cs enb2 enb1 ena1 ena2 bclk/c4i config1 config2 ic sin rin nlp vss rev mclk format law pwrdn td2 td1 s4/sclk s3/cs s2/data2 vdd f0od s1/data1 sout rout f0i plcc 4 5 6 7 8 9 10 11 25 24 23 22 21 20 19 ? 3 2 1 2 8 2 7 2 6 1 2 1 3 1 4 1 5 1 6 1 7 1 8 pdip
data sheet MT9122 3 5 rin receive pcm signal input (input). 128 kbit/s to 4096 kbit/s serial pcm input stream. data may be in either companded or 2?s complement linear format. two pcm channels are time- multiplexed on this pin. these are the receive input reference channels for echo cancellers a and b. data bits are clocked in following ssi or st-bus timing requirements. 6 sin send pcm signal input (input). 128 kbit/s to 4096 kbit/s serial pcm input stream. data may be in either companded or 2?s complement linear format. two pcm channels are time- multiplexed on this pin. these are the send input channels (after echo path) for echo cancellers a and b. data bits are clocked in following ssi or st-bus timing requirements. 7 vss digital ground: nominally 0 volts. 8 mclk master clock (input): nominal 20 mhz master clock input. may be connected to an asynchronous (relative to frame signal) clock source. 9 ic internal connection (input): must be tied to vss. 10 nlp non-linear processor control (input): controllerless mode : an active high enables the non-linear processors in echo cancellers a and b. both nlp?s are disabled when low. intended for conformance testing to g.165 and it is usually tied to vdd for normal operation. controller mode : this pin is ignored (tie to vdd or vss). the non-linear processor operation is controlled by the nlpdis bit in control register 2. refer to the register summary. 11 rev reversal detection (input): controllerless mode : an active high configures all the tone detectors to trigger only when a 2100hz disable tone with periodic phase reversal is present (per g.165). when low, the tone detectors will trigger upon detection of any 2100hz disable tone, with or without periodic phase reversal (per g.164). controller mode : this pin is ignored (tie to vdd or vss). the operation is controlled by the phdis bit in control register 2. refer to the register summary. 12 law a/ law select (input): an active low selects ? law companded pcm. when high, selects a-law companded pcm. this control is for both echo cancellers and is valid for both controller and controllerless modes. 13 format itu-t/sign mag (input): an active low selects sign-magnitude pcm code. when high, selects itu-t (g.711) pcm code. this control is for both echo cancellers and is valid for both controller and controllerless modes. 14 pwrdn power-down (input): an active low resets the device and puts the MT9122 into a low-power stand-by mode. 15 td2 tone detect 2 (output): an active low output occurs when echo canceller b detects the presence of a valid 2100hz disabling tone (g.164 or g.165) on rin or sin pins. this output returns to a logic high once the release criteria are met. the behavior of this pin is identical in both controller and controllerless modes. 16 td1 tone detect 1 (output): an active low output occurs when echo canceller a detects the presence of a valid 2100hz disabling tone (g.164 or g.165) on rin or sin pins. this output returns to a logic high once the release criteria are met. the behavior of this pin is identical in both controller and controllerless modes. pin description (continued) pin # name description
4 MT9122 data sheet notes: 1. all unused inputs should be connected to logic low or high unless otherwise stated. all outputs should be left open circuit w hen not used. 2. all inputs have ttl compatible logic levels except for mclk, sin and rin pins which have cmos compatible logic levels and pwr dn pin which has schmitt trigger compatible logic levels. 3. all outputs are cmos pins with cmos logic levels. 17/18 17 18 s4/s3 sclk cs selection of echo canceller b functional states (input): controllerless mode : selects echo canceller b functional states according to table 2. controller mode : s4 and s3 pins become sclk and cs pins respectively. serial port synchronous clock (input): data clock for the serial microport interface. chip select (input): enables serial microport interface data transfers. active low. 19/20 19 20 s2/s1 data2 data1 selection of echo canceller a functional states (input): controllerless mode : selects echo canceller a functional states according to table 2. controller mode : s2 and s1 pins become data2 and data1 pins respectively. serial data receive (input): in motorola/national serial microport operation, the data2 pin is used for receiving data. in intel serial microport operation, the data2 pin is not used and must be tied to vss or vdd. serial data port (bidirectional): in motorola/national serial microport operation, the data1 pin is used for transmitting data. in intel serial microport operation, the data1 pin is used for transmitting and receiving data. 21 f0od delayed frame pulse output (output): in st-bus operation, this pin generates a delayed frame pulse after the 4th channel time slot and is used for daisy-chaining multiple st-bus devices. see figures 5 to 8. in ssi operation, this pin outputs logic low. 22 vdd positive power supply: nominally 5 volts. 23 sout send pcm signal output (output): 128 kbit/s to 4096 kbit/s serial pcm output stream. data may be in either companded or 2?s complement linear pcm format. two pcm channels are time-multiplexed on this pin. these are the send out signals after echo cancellation and non-linear processing. data bits are clocked out following ssi or st-bus timing requirements. 24 rout receive pcm signal output (output): 128 kbit/s to 4096 kbit/s serial pcm output stream. data may be in either companded or 2?s complement linear pcm format. two pcm channels are time-multiplexed on this pin. this output pin is provided for convenience in some applications and may not always be required. data bits are clocked out following ssi or st-bus timing requirements. 25 f0i frame pulse (input): in st-bus operation, this is a frame alignment low going pulse. ssi operation is enabled by connecting this pin to vss. 26 bclk/c4i bit clock/st-bus clock (input): in ssi operation, bclk pin is a 128 khz to 4.096 mhz bit clock. this clock must be synchronous with ena1, ena2, enb1 and enb2 enable strobes. in st-bus operation, c4i pin must be connected to the 4.096mhz (c4 ) system clock. 27/28 config1/ config2 device configuration pins (inputs). when config1 and config2 pins are both logic 0, the MT9122 serial microport is enabled. this configuration is defined as controller mode . when config1 and config2 pins are in any other logic combination, the MT9122 is configured in controllerless mode . see table 3. pin description (continued) pin # name description
data sheet MT9122 5 functional description the MT9122 architecture contains two individually controlled echo cancellers (echo canceller a and b). they can be set in three distinct configurations: normal, back-to-back and extended delay (see figure 3). under normal configuration, the two echo cancellers are positioned in parallel providing 64 millisecond echo cancellation in two channels simultaneously. in back-to-back configuration, the two echo cancellers are positioned to cancel echo coming from both directions in a single channel. in extended-delay configuration, the two echo cancellers are internally cascaded into one 128 millisecond echo canceller. each echo canceller contains the following main elements (see figure 1). ? adaptive filter for estimating the echo channel ? subtracter for cancelling the echo ? double-talk detector for disabling the filter adaptation during periods of double-talk ? non-linear processor for suppression of residual echo ? disable tone detectors for detecting valid disable tones at the input of receive and send paths ? narrow-band detector for preventing adaptive filter divergence caused by narrow-band signals ? offset null filters for removing the dc component in pcm channels ? 12db attenuator for signal attenuation ? serial controller interface compatible with motorola, national and intel microcontrollers ? pcm encoder/decoder compatible with /a-law itu-t g.711, /a-law sign-mag or linear 2?s complement coding the MT9122 has two modes of operation: controllerless and controller . controllerless mode is intended for applications where customization is not required. controller mode allows access to all registers for customizing the MT9122 operation. refer to table 7 for a complete list. controller mode is selected when config1 and config2 pins are both connected to vss. each echo canceller in the MT9122 has four functional states: mute , bypass , disable adaptation and enable adaptation . these are explained in the section entitled echo canceller functional states. figure 3 - device configuration rin rout sout sin echo path a optional -12db pad port 2 port 1 echo path b + - channel a channel a + - channel b channel b e.c.a e.c.b a) normal configuration (64ms) + - channel a channel a e.c.a sin sout rout rin b) extended delay configuration (128ms) port 2 port 1 + e.c.a sin sout rout rin c) back-to-back configuration (64ms) - e.c.b + - echo echo path path port 2 port 1 echo path a adaptive filter (64ms) adaptive filter (64ms) optional -12db pad adaptive filter (64ms) optional -12db pad adaptive filter (64ms) optional -12db pad adaptive filter (128 ms) optional -12db pad
6 MT9122 data sheet adaptive filter the adaptive filter is a 1024 tap fir filter which is divided into two sections. each section contains 512 taps providing 64ms of echo estimation. in normal configuration, the first section is dedicated to channel a and the second section to channel b. in extended delay configuration, both sections are cascaded to provide 128ms of echo estimation in channel a. double-talk detector double-talk is defined as those periods of time when signal energy is present in both directions simultaneously. when this happens, it is necessary to disable the filter adaptation to prevent divergence of the adaptive filter coefficients. note that when double-talk is detected, the adaptation process is halted but the echo canceller continues to cancel echo. a double-talk condition exists whenever the sin signal level is greater than the expected return echo level. the relative signal levels of rin (lrin) and sin (lsin) are compared according to the following expression to identify a double-talk condition: lsin > lrin + 20log 10 (dtdt) where dtdt is the double-talk detection threshold. lsin and lrin are the relative signal levels expressed in dbm0. a different method is used when it is uncertain whether sin consists of a low level double-talk signal or an echo return. during these periods, the adaptation process is slowed down but it is not halted. controllerless mode in g.165 standard, the echo return loss is expected to be at least 6db. this implies that the double-talk detector threshold (dtdt) should be set to 0.5 (-6db). however, in order to get additional guardband, the dtdt is set internally to 0.5625 (- 5db). in controllerless mode, the double-talk detector is always active. controller mode in some applications the return loss can be higher or lower than 6db. the MT9122 allows the user to change the detection threshold to suit each application?s need. this threshold can be set by writing the desired threshold value into the dtdt register. the dtdt register is 16 bits wide. the register value in hexadecimal can be calculated with the following equation: dtdt (hex) = hex(dtdt (dec) * 32768) where 0 < dtdt (dec) < 1 example: for dtdt = 0.5625 (-5db), the hexadecimal value becomes hex( 0.5625 * 32768 ) = 4800h non-linear processor (nlp) after echo cancellation, there is always a small amount of residual echo which may still be audible. the MT9122 uses an nlp to remove residual echo signals which have a level lower than the adaptive suppression threshold (tsup in g.165). this threshold depends upon the level of the rin (lrin) reference signal as well as the programmed value of the non-linear processor threshold register (nlpthr). tsup can be calculated by the following equation: tsup = lrin + 20log 10 (nlpthr) where nlpthr is the non-linear processor threshold register value and lrin is the relative power level expressed in dbm0. when the level of residual error signal falls below tsup, the nlp is activated further attenuating the residual signal to less than -65dbm0. to prevent a perceived decrease in background noise due to the activation of the nlp, a spectrally-shaped comfort noise, equivalent in power level to the background noise, is injected. this keeps the perceived noise level constant. consequently, the user does not hear the activation and de-activation of the nlp. controllerless mode the nlp processor can be disabled by connecting the nlp pin to vss. controller mode the nlp processor can be disabled by setting the nlpdis bit to 1 in control register 2. the nlpthr register is 16 bits wide. the register value in hexadecimal can be calculated with the following equation: nlpthr (hex) = hex(nlpthr (dec) * 32768)
data sheet MT9122 7 where 0 < nlpthr (dec) < 1 the comfort noise injection can be disabled by setting the injdis bit to 1 in control register 1. it should be noted that the nlpthr is valid and the comfort noise injection is active only when the nlp is enabled. disable tone detector g.165 recommendation defines the disable tone as having the following characteristics: 2100 hz ( 21hz) sinewave, a power level between -6 to -31dbm0, and a phase reversal of 180 degrees ( 25 degrees) every 450ms ( 24ms). if the disable tone is present for a minimum of one second with at least one phase reversal, the tone detector will trigger. g.164 recommendation defines the disable tone as a 2100 hz ( 21hz) sinewave with a power level between -6 to -31dbm0. if the disable tone is present for a minimum of one second, with or without phase reversal, the tone detector will trigger. the MT9122 has four tone detectors in order to monitor the occurrence of a valid disable tone on channels a and b on both rin and sin. upon detection of a disable tone, output pins td1 or td2 will go low as illustrated in figure 4. figure 4 - disable tone detection once a tone detector has been triggered, the MT9122 no longer needs a valid disable tone (g.164 or g.165) to maintain tone detector status (e.g. td1 , td2 pins low). the tone detector status will only release (e.g. td1 , td2 pins high) if the signals rin and sin fall below -30dbm0, in the frequency range of 390hz to 700hz, and below -34dbm0, in the frequency range of 700hz to 3400hz, for at least 400ms. controllerless mode the selection between g.165 and g.164 tone disable is controlled by the rev pin. when the rev pin is connected to vss, g.164 is selected. this applies to all four tone detectors. in response to a valid disable tone, the MT9122 must be switched from the enable adaptation state to the bypass state. in an application, the tone detect outputs, td1 and td2, may be used to switch the echo cancellers between these two states. this is achieved by connecting s1 and s3 pins to vdd and by connecting the td1 and td2 outputs to the s2 and s4 input pins respectively. controller mode the selection between g.165 and g.164 tone disable is controlled by the phdis bit in control register 2. when the phdis bit is set to 1, g.164 tone disable requirements are selected. this applies to all four tone detectors. in response to a valid disable tone, the MT9122 must be switched from the enable adaptation state to the bypass state. this can be done in two ways, automatically or externally. in automatic mode, the tone detectors internally control the switching between enable adaptation and bypass states. the automatic mode can be activated by setting the autotd bit in control register 2 to high. in external mode, an external controller is needed to poll the td bit in status register a or b. following the detection of a disable tone (td bit high), the external controller should switch the echo canceller from enable adaptation to bypass state. the td1 and td2 output pins remain active, as in controllerless mode, and they can be used as an interrupt to an external controller. narrow band signal detector (nbsd) single or dual frequency tones (e.g. dtmf tones) present in the reference input (rin) of the echo canceller for a prolonged period of time may cause the adaptive filter to diverge. the narrow band signal detector (nbsd) is designed to prevent this divergence by detecting single or dual tones of arbitrary frequency, phase, and amplitude. when narrow band signals are detected, the adaptation process is halted but the echo canceller continues to cancel echo. td1 rin sin echo canceller a tone detector tone detector echo canceller b td2 rin sin tone detector tone detector
8 MT9122 data sheet controllerless mode the nbsd is always active and automatically disables the filter adaptation process when narrow band signals are detected. controller mode the nbsd can be disabled by setting the nbdis bit to 1 in control register 2. offset null filter adaptive filters in general do not operate properly when a dc offset is present on either the reference signal (rin) or the echo composite signal (sin). to remove the dc component, the MT9122 incorporates offset null filters in both rin and sin inputs. controllerless mode the offset null filters are always active. controller mode the offset null filters can be disabled by setting the hpfdis bit to 1 in control register 2. echo canceller functional states each echo canceller has four functional states: mute, bypass, disable adaptation and enable adaptation. mute : the mute state forces the echo canceller to transmit quiet code and halts the filter adaptation process. in normal configuration, the pcm output data on rout is replaced with the quiet code according to the following table. in back-to-back configuration, both echo cancellers are combined to implement a full duplex echo canceller. therefore muting echo canceller a causes quiet code to be transmitted on rout, while muting echo canceller b causes quiet code to be transmitted on sout. in extended delay configuration, both echo cancellers are cascaded to make one 128ms echo canceller. in this configuration, muting echo canceller a causes quiet code to be transmitted on rout. bypass : the bypass state directly transfers pcm codes from rin to rout and from sin to sout. when bypass state is selected, the adaptive filter coefficients are reset to zero. disable adaptation : when the disable adaptation state is selected, the adaptive filter coefficients are frozen at their current value. in this state, the adaptation process is halted however the MT9122 continues to cancel echo. enable adaptation : in enable adaptation state, the adaptive filter coefficients are continually updated. this allows the echo canceller to model the echo return path characteristics in order to cancel echo. this is the normal operating state. controllerless mode the four functional states can be selected via s1, s2, s3, and s4 pins as shown in the following table. (1) filter coefficients are frozen (adaptation disabled) (2) the adaptive filter coefficients are reset to zero (3) the MT9122 cancels echo table 2 - functional states control pins controller mode the echo canceller functions are selected in control register 1 and control register 2 through four control bits: mutes, muter, bypass and adaptdis. see register summary for details. MT9122 throughput delay the throughput delay of the MT9122 varies according to the data path and the device configuration. for all device configurations, except linear 16 bits 2?s complement sign/ magnitude -law a-law ccitt (g.711) -law a-law +zero (quiet code) 0000h 80h ffh d5h table 1 - quiet pcm code assignment echo canceller a s2/s1 functional state echo canceller b s4/s3 00 mute (1) 00 01 bypass (2) 01 10 disable adaptation (1,3) 10 11 enable adaptation (3) 11
data sheet MT9122 9 for bypass state, rin to rout has a delay of two frames and sin to sout has a delay of three frames. in bypass state, the rin to rout and sin to sout paths have a delay of two frames. in st-bus operation, the d and c channels have a delay of one frame. power down forcing the pwrdn pin to logic low, will put the MT9122 into a power down state. in this state all internal clocks are halted, the data1, sout and rout pins are tristated and the f0od , td1 , and td2 pins output high. the device will automatically begin the execution of its initialization routines when the pwrdn pin is returned to logic high and a clock is applied to the mclk pin. the initialization routines execute for one frame and will set the MT9122 to default register values. device configuration the MT9122 architecture contains two individually controlled echo cancellers (echo canceller a and b). they can be set in three distinct configurations: normal, back-to-back, and extended delay. see figure 3. normal configuration : in this configuration, the two echo cancellers (echo canceller a and b) are positioned in parallel, as shown in figure 3a, providing 64 milliseconds of echo cancellation in two channels simultaneously. in ssi operation, both channels are available in different timeslots on the same tdm (time division multiplexing) bus. for echo canceller a, the ena1 enable strobe pin defines the rin/sout (port1) time slot while the ena2 enable strobe pin defines the sin/rout (port2) time slot. the enb1 and enb2 enable strobes perform the same function for echo canceller b. in st-bus operation, the ena1, ena2, enb1 and enb2 pins are used to determine the pcm data format and the channel locations. see table 4. back-to-back configuration : in this configuration, the two echo cancellers are positioned to cancel echo coming from both directions in a single channel providing full duplex 64 millisecond echo-cancellation. see figure 3c. this configuration uses only one timeslot on port1 and port2, allowing a no-glue interface for applications where bidirectional echo cancellation is required. in ssi operation, ena1 and ena2 enable pins are used to strobe data on rin/sout and sin/rout respectively. in st-bus operation, ena1, ena2, enb1 and enb2 inputs are used to select the st- bus mode according to table 4. examples of back-to-back configuration include positioning the MT9122 between a codec and a transmission device or between two codecs for echo control on analog trunks. extended delay configuration : in this configuration, the two echo cancellers are internally cascaded into one 128 millisecond echo canceller. see figure 3b. in ssi operation, ena1 and ena2 enable pins are used to strobe data on rin/sout and sin/rout respectively. in st-bus operation, ena1, ena2, enb1 and enb2 inputs are used to select the st-bus mode according to table 4. controllerless mode the three configurations can be selected through the config1 and config2 pins as shown in the following table. table 3 - configuration in controllerless mode controller mode in control register 1, the normal configuration can be programmed by setting both bbm and extended- delay bits to 0. back-to-back configuration can be programmed by setting the bbm bit to 1 and extended-delay bit to 0. extended-delay configuration can be programmed by setting the extended-delay bit to 1 and bbm bit to 0. both bbm and extended-delay bits in control register 1 can not be set to 1 at the same time. pcm data i/o the pcm data transfer for the MT9122 is provided through two pcm ports. port1 consists of rin and sout pins while port2 consists of sin and rout pins. the data is transferred through these ports according to either st-bus or ssi conventions. the config1 config2 configuration 00 (selects controller mode) 0 1 extended delay mode 1 0 back-to-back mode 1 1 normal mode
10 MT9122 data sheet device determines the mode of operation by monitoring the signal applied to the f0i pin. when a valid st-bus frame pulse is applied to the f0i pin, the MT9122 will assume st-bus operation. if f0i is tied continuously to vss the MT9122 will assume ssi operation. st-bus operation the st-bus pcm interface conforms to zarlink?s st-bus standard and it is used to transport 8 bit companded pcm data (using one timeslot) or 16 bit 2?s complement linear pcm data (using two timeslots). pins ena1 and enb1 select timeslots on port1 while pins ena2 and enb2 select timeslots on port2. see table 4 and figures 5 to 8. table 4 - st-bus mode select note that if the device is in back-to-back or extended delay configurations, the second timeslot in any st- bus mode contains undefined data. this means that the following timeslots contain undefined data: timeslot 1 in st-bus mode 1; timeslot 3 in st-bus modes 2 & 3 and timeslots 2 and 3 in st-bus mode 4. ssi operation the ssi pcm interface consists of data input pins (rin, sin), data output pins (sout, rout), a variable rate bit clock (bclk), and four enable pins (ena1,enb1, ena2 and enb2) to provide strobes for data transfers. the active high enable may be either 8 or 16 bclk cycles in duration. automatic detection of the data type (8 bit companded or 16 bit 2?s complement linear) is accomplished internally. the data type cannot change dynamically from one frame to the next. port1 rin/sout st-bus mode selection port2 sin/rout enable pins enable pins enb1 ena1 enb2 ena2 0 0 mode 1 . 8 bit companded pcm i/o on timeslots 0 & 1. 00 0 1 mode 2 . 8 bit companded pcm i/o on timeslots 2 & 3. 01 1 0 mode 3 . 8 bit companded pcm i/o on timeslots 2 & 3. includes d & c chan- nel bypass in timeslots 0 & 1. 10 1 1 mode 4 . 16 bit 2?s complement linear pcm i/o on timeslots 0 - 3. 11 in ssi operation, the frame boundary is determined by the rising edge of the ena1 enable strobe (see figure 9). the other enable strobes (enb1, ena2 and enb2) are used for parsing input/output data and they must pulse within 125 microseconds of the rising edge of ena1. if they are unused, they must be tied to vss. in ssi operation, the enable strobes may be a mixed combination of 8 or 16 bclk cycles allowing the flexibility to mix 2?s complement linear data on one port (e.g., rin/sout) with companded data on the other port (e.g., sin/rout). table 5 - ssi enable strobe pins pcm law and format control (law, format) the pcm companding/coding law used by the MT9122 is controlled through the law and format pins. itu-t g.711 companding curves for -law and a-law are selected by the law pin. pcm coding itu-t g.711 and sign-magnitude are selected by the format pin. see table 6. linear pcm the 16-bit 2?s complement pcm linear coding permits a dynamic range beyond that which is specified in itu-t g.711 for companded pcm. the echo-cancellation algorithm will accept 16 bits 2?s complement linear code which gives a dynamic range of +15dbm0. note however that the tone enable strobe pin echo canceller port ena1 a 1 enb1 b 1 ena2 a 2 enb2 b 2 pcm code sign-magnitude format=0 itu-t (g.711) format=1 /a-law law = 0 or 1 -law law = 0 a-law law =1 + full scale 1111 1111 1000 0000 1010 1010 + zero 1000 0000 1111 1111 1101 0101 - zero 0000 0000 0111 1111 0101 0101 - full scale 0111 1111 0000 0000 0010 1010 table 6 - companded pcm
data sheet MT9122 11 detectors must be limited to the maximum dynamic range specified in g.711 (+3.14 or +3.17 dbm0). linear pcm data must be formatted as 14-bit, 2?s complement data with three bits of sign extension in the most significant positions (i.e.: s,s,s,12,11, ...1,0) for a total of 16 bits where ?s? is the extended sign bit. when a-law is converted to 2?s complement linear format, it must be scaled up by 6db (i.e. left shifted one bit) with a zero inserted into the least significant bit position. see figure 8. bit clock (bclk/c4i ) the bclk/c4i pin is used to clock the pcm data in both ssi (bclk) and st-bus (c4i ) operations. in ssi operation, the bit rate is determined by the bclk frequency. this input must contain either eight or sixteen clock cycles within the valid enable strobe window. bclk may be any rate between 128 khz to 4.096 mhz and can be discontinuous outside of the enable strobe windows defined by ena1, enb1, ena2 and enb2 pins. incoming pcm data (rin, sin) are sampled on the falling edge of bclk while outgoing pcm data (sout, rout) are clocked out on the rising edge of bclk. see figure 17. in st-bus operation, connect the system c4 (4.096mhz) clock to the c4i pin. master clock (mclk) a nominal 20mhz master clock (mclk) is required for execution of the MT9122 algorithms. the mclk input may be asynchronous with the 8khz frame. if only one channel operation is required, (echo canceller a only) the mclk can be as low as 9.6mhz. microport the serial microport provides access to all MT9122 internal read and write registers and it is enabled when config1 and config2 pins are both set to logic 0. this microport is compatible with intel mcs- 51 (mode 0), motorola spi (cpol=0, cpha=0), and national semiconductor microwire specifications. the microport consists of a transmit/receive data pin (data1), a receive data pin (data2), a chip select pin (cs ) and a synchronous data clock pin (sclk). the MT9122 automatically adjusts its internal timing and pin configuration to conform to intel or motorola/ national requirements. the microport dynamically senses the state of the sclk pin each time cs pin becomes active (i.e. high to low transition). if sclk pin is high during cs activation, then intel mode 0 timing is assumed. in this case data1 pin is defined as a bi-directional (transmit/receive) serial port and data2 is internally disconnected. if sclk is low during cs activation, then motorola/national timing is assumed and data1 is defined as the data transmit pin while data2 becomes the data receive pin. the MT9122 supports motorola half-duplex processor mode (cpol=0 and cpha=0). this means that during a write to the MT9122, by the motorola processor, output data from the data1 pin must be ignored. this also means that input data on the data2 pin is ignored by the MT9122 during a valid read by the motorola processor. all data transfers through the microport are two bytes long. this requires the transmission of a command/ address byte followed by the data byte to be written or read from the addressed register. cs must remain low for the duration of this two-byte transfer. as shown in figures 10 and 11, the falling edge of cs indicates to the MT9122 that a microport transfer is about to begin. the first 8 clock cycles of sclk after the falling edge of cs are always used to receive the command/address byte from the microcontroller. the command/address byte contains information detailing whether the second byte transfer will be a read or a write operation and at what address. the next 8 clock cycles are used to transfer the data byte between the MT9122 and the microcontroller. at the end of the two-byte transfer, cs is brought high again to terminate the session. the rising edge of cs will tri-state the data1 pin. the data1 pin will remain tri-stated as long as cs is high. intel processors utilize least significant bit (lsb) first transmission while motorola/national processors use most significant bit (msb) first transmission. the MT9122 microport automatically accommodates these two schemes for normal data bytes. however, to ensure timely decoding of the r/w and address information, the command/address byte is defined differently for intel and motorola/national operations. refer to the relative timing diagrams of figures 10 and 11. receive data is sampled on the rising edge of sclk while transmit data is clocked out on the falling edge of sclk. detailed microport timing is shown in figure 19 and figure 20.
12 MT9122 data sheet function controllerless selected when pins config1 & 2 00 controller selected when pins config1 & 2 = 00 normal configuration set pins config1 to 1 and config2 1 to select this configuration. set bits extended-delay to 0 and bbm to 0 in control reg- ister 1 to select. back-to-back configuration set pins config1 to 1 and config2 to 0 to select this configuration. set bit bbm to 1 in control register 1 to select. extended delay configuration set pins config1 to 0 and config2 to 1 to select this configuration. set bit extended-delay to 1 in control register 1 to select. mute set pins s2/s1 to 00 and s4/s3 to 00 to select for echo canceller a and echo canceller b respectively. set bit muter to 1 or mutes to 1 in control register 2 to select. bypass set pins s2/s1 to 01 and s4/s3 to 01 to select for echo canceller a and echo canceller b, respectively. set bit bypass to 1 in control register 1 to select. disable adaptation set pins s2/s1 to 10 and s4/s3 to 10 to select for echo canceller a and echo canceller b, respectively. set bit adaptdis to 1 in control register 1 to select. enable adaptation set pins s2/s1 to 11 and s4/s3 to 11 to select for echo canceller a and echo canceller b, respectively. set bits adaptdis to 0 and bypass to 0 in control register 1 to select. ssi tie pin f0i to vss to select. tie pin f0i to vss to select. st-bus apply a valid st-bus frame pulse to f0i pin to select. apply a valid st-bus frame pulse to f0i pin to select. 12db attenuator always disabled. set bit pad to 1 in control register 1 to enable. double-talk detector continuously enabled which disables filter adaptation when double-talk is detected. the detection threshold can be controlled via double-talk detection threshold register 1 and 2. disable tone detector it is continuously enabled and puts td1 or td2 or both into active low when disable tone is detected. the td1 and td2 outputs have to be externally manipulated by the user to bypass the echo canceller. set bit tdis to 1 in control register 2 to disable tone detectors. disable tone set pin rev to 1 to select disable tone with phase reversal (g.165). set bit phdis to 1 in control register 2 to select disable tone without phase reversal (g164). non-linear processor set pin nlp to 1 to enable. set bit nlpdis to 1 to disable. pcm law set pin law to 1 or 0 to select a-law or -law respectively. set pin law to 1or 0 to select a-law or -law respectively. pcm format set pin format to 0 or 1 to select sign-magnitude or itu-t format respectively. set pin format to 0 or 1 to select sign-magnitude or itu-t format respectively. narrow-band signal detector continuously enabled which disables the filter adapta- tion when narrow band signal is detected. set bit nbdis to 1 in control register 2 to disable. offset null filter continuously enabled which removes the dc compo- nent in the pcm input. set bit hpfdis to 1 in control register 2 to disable. table 7 - MT9122 function control summary
data sheet MT9122 13 figure 5 - st-bus 8 bit companded pcm i/o on timeslots 0 & 1 (mode 1) figure 6 - st-bus 8 bit companded pcm i/o on timeslots 2 & 3 (mode 2) c4i f0i sin rout rin sout f0od 76 54 7654 3210 3 210 76 54 7654 3210 3 210 76 54 76 54 3210 3 210 76 54 7654321 0 3210 outputs=high impedance inputs = don?t care eca ecb in st-bus mode 1, both echo canceller i/o channels are assigned to st-bus timeslots 0 and 1. note that the user could configure port1 and port2 into different st-bus modes. the pin f0od is always delayed 4 time slots to permit a more flexible interleave of st-bus modes. port1 port2 01 2 34 eca ecb c4i f0i sin rout rin sout f0od 76 54 76 543210 3210 76 54 76 543210 3210 76 54 76 543210 3210 76 54 76 54321 0 321 0 eca ecb in st-bus mode 2, both echo canceller i/o channels are assigned to st-bus timeslots 2 and 3. note that the user could configure port1 and port2 into different st-bus modes. the pin f0od is always delayed 4 time slots to permit a more flexible interleave of st-bus modes. eca ecb port1 port2 01 2 34 outputs=high impedance inputs = don?t care
14 MT9122 data sheet figure 7 - st-bus 8 bit companded pcm i/o with d and c channels (mode 3) figure 8 - st-bus 16 bit 2?s complement linear pcm i/o (mode 4) c4i f0i rin sout eca ecb f0od sin rout eca ecb port1 port2 indicates that an input channel is bypassed to an output channel st-bus mode 3 supports connection to 2b+d devices where timeslots 0 and 1 transport d and c channels and both echo canceller i/o channels are assigned to st-bus timeslots 2 and 3. both port1 and port2 must be configured in st-bus mode 3. 01 2 34 outputs=high impedance inputs = don?t care 76 54 3210 7654321 0 7654321 0 76 543 210 76 54 3210 76 54321 0 76 54321 0 76 543 210 76 54 3210 7654321 0 7654321 0 76 543 210 76 54 3210 76 54321 0 76 54321 0 76 543 210 c4i f0i rin sout eca ecb f0od 76543210 sin rout port1 port2 ss s12 111098 76543210 ss s12 11 10 9 8 76543210 ss s 12 11 10 9 8 7 6 5 4 3 2 1 0 ss s 12 11 10 9 8 eca ecb 76543210 ss s1211109 8 7 6 5 4 3 2 1 0 ss s1211109 8 76543210 s s s 12 11 10 9 8 7 6 5 4 3 2 1 0 s s s 12 11 10 9 8 st-bus mode 4 allows 16 bits 2?s complement linear data to be transferred using st-bus i/o timing. note that port1 and port2 need not necessarily both be in mode 4. outputs=high impedance inputs = don?t care
data sheet MT9122 15 figure 9 - ssi operation figure 10 - serial microport timing for intel mode 0 bclk ena1 enb1 rin sout eca ecb 8 or 16 bits 8 or 16 bits 8 or 16 bits 8 or 16 bits port1 port2 eca ecb 8 or 16 bits 8 or 16 bits 8 or 16 bits 8 or 16 bits ena2 enb2 sin rout note that the two ports are independent so that, for example, port1 can operate with 8 bit enable strobes and port2 can operate with 16 bit enable strobes. outputs=high impedance inputs = don?t care r/w a 0 a 1 a 2 a 3 a 4 a 5 x command/address data input/output data 1 sclk cs ? ? ? ? ? ? ? ? ? ? delays due to internal processor timing which are transparent to the MT9122. the MT9122: outputs transmit data on the falling edge of sclk the falling edge of cs indicates that a command/address byte will be transmitted from the microprocessor. the subsequent byte is always data followed by cs returning high. a new command/address byte may be loaded only by cs cycling high then low again. the command/address byte contains: 1 bit - read/write 6 bits - addressing data 1 bit - unused d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 latches receive data on the rising edge of sclk
16 MT9122 data sheet figure 11 - serial microport timing for motorola mode 00 or national microwire x a 0 a 1 a 2 a 3 a 4 a 5 r/w command/address data input data 2 receive data 1 transmit sclk cs ? ? ? ? ? ? ? ? ? delays due to internal processor timing which are transparent to the MT9122. the falling edge of cs indicates that a command/address byte will be transmitted from the microprocessor. the subsequent byte is always data followed by cs returning high. a new command/address byte may be loaded only by cs cycling high then low again. the command/address byte contains: 1 bit - read/write 6 bits - addressing data 1 bit - unused d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 high impedance data output ? the MT9122: outputs transmit data on the falling edge of sclk latches receive data on the rising edge of sclk
data sheet MT9122 17 register summary extended- when high, echo cancellers a and b are internally cascaded into one 128ms echo canceller. when low, echo cancellers a and b operate independently. do not enable both extended-delay and bbm configurations at the same time. adaptdis when high, echo canceller adaptation is disabled. when low, the echo canceller dynamically adapts to the echo path characteristics. bypass when high, sin data is by-passed to sout and rin data is by-passed to rout. when low, output data on both sout and rout is a function of the echo canceller algorithm. pad when high, 12db of attenuation is inserted into the rin to rout path. when low the rin to rout path gain is 0db. bbm when high the back to back configuration is enabled. when low the normal configuration is enabled. do not enable extended-delay and bbm configurations at the same time. always set both bbm bits of the two echo cancellers to the same logic value to avoid conflict. injdis when high, the noise injection process is disabled. when low noise injection is enabled. reset when high, the power-up initialization is executed presetting all register bits including this bit. note: bits marked as ?1? or ?0? are reserved bits and should be written as indicated. echo canceller a, control register 1 address = 00h write/read verify power reset value 0000 0000 76543210 injdis bbm pad adaptdis 0 extended bypass reset power reset value 0000 0010 76543210 injdis bbm pad adaptdis 1 0 bypass reset echo canceller b, control register 1 address = 20h write/read verify delay delay cra1 crb1 muter when high, data on rout is muted to quiet code. when low, rout carries active code. mutes when high, data on sout is muted to quiet code. when low, sout carries active code. hpfdis when high, the offset nulling high pass filters are bypassed in the rin and sin paths. when low, the offset nulling filters are active and will remove dc offsets on pcm input signals. nbdis when high, the narrow-band detector is disabled. when low, the narrow-band detector is enabled. autotd when high, the echo canceller is in bypass mode when the tone detectors detect the presence of 2100hz tones. see phdis for qualification of 2100hz tones. when low, the echo canceller algorithm will remain operational regardless of the state of the 2100hz tone detectors. nlpdis when high, the non-linear processor is disabled. when low, the non-linear processors function normally. useful for g.165 conformance testing. phdis when high, the tone detectors will trigger upon the presence of a 2100hz tone regardless of the presence/absence of period ic phase reversals. when low, the tone detectors will trigger only upon the presence of a 2100hz tone with periodic phase reversals. tdis when high, tone detection is disabled entirely. when low, tone detection is enabled. echo canceller a, control register 2 address = 01h write/read verify power reset value 0000 0000 76543210 phdis nlpdis autotd hpfdis mutes muter echo canceller b, control register 2 address = 21h write/read verify nbdis tdis cr2 nb logic high indicates the presence of a narrow-band signal on rin. tdg tone detection status bit gated with the autotd bit. logic high indicates that autotd has been enabled and the tone detector has detected the presence of a 2100hz tone. active logic high indicates that the power level on rin is above the threshold level (i.e., low power condition). down decision indicator for the non-linear processor gain adjustment. conv decision indicator for rapid adaptation convergence. logic high indicates a rapid convergence state. dtdet logic high indicates the presence of a double-talk condition. td logic high indicates the presence of a 2100hz tone. power reset value 0000 0000 76543210 td dtdet conv active tdg nb echo canceller a, status register address = 02h read echo canceller b, status register address = 22h read down sr
18 MT9122 data sheet power reset value 00h 76543210 fd 7 fd 6 fd 5 fd 4 fd 2 fd 1 fd 0 fd 3 echo canceller a, flat delay register address = 04h write/read verify echo canceller b, flat delay register address = 24h write/read verify power reset value 00h 76543210 ns 7 ns 6 ns 5 ns 4 ns 2 ns 1 ns 0 ns 3 echo canceller a, decay step number register address = 07h write/read verify echo canceller b, decay step number register address = 27h write/read verify power reset value 04h 76543210 0000 ssc 2 ssc 1 ssc 0 0 echo canceller a, decay step size control register address = 06h write/read verify echo canceller b, decay step size control register address = 26h write/read verify note: bits marked with ?0? are reserved bits and should be written ?0?. ssc ns amplitude of mu time flat delay (fd 7-0 ) step size (ss) 1.0 2 -16 fir filter length (512 or 1024 taps) number of steps (ns 7-0 ) the exponential decay registers (decay step number and decay step size) and flat delay register allow the lms adaptation step-size (mu) to be programmed over the length of the fir filter. a programmable mu profile allows the performance of the echo canceller to be optimized for specific applications. for example, if the characteristic of the echo response is known to have a flat delay of several milliseconds and a roughly exponential decay of the echo impulse response, then the mu profile can be programmed to approximate this expected impulse response thereby improving the convergence characteristics of the adaptive filter. note that in the following register descriptions, one tap is equivalent to 125 s (64ms/512 taps). fd 7-0 flat delay : this register defines the flat delay of the mu profile, (i.e., where the mu value is 2 -16 ). the delay is defined as fd 7-0 x 8 taps. for example; if fd 7-0 = 5, then mu=2 -16 for the first 40 taps of the echo canceller fir filter. the valid range of fd 7-0 is: 0 <= fd 7-0 <= 64 in normal mode and 0 <= fd 7-0 <= 128 in extended-delay mode. the default value of fd 7-0 is zero. ssc 2-0 decay step size control : this register controls the step size (ss) to be used during the exponential decay of mu. the decay rate is defined as a decrease of mu by a factor of 2 every ss taps of the fir filter, where ss = 4 x2 ssc 2-0 . for example; if ssc 2-0 = 4, then mu is reduced by a factor of 2 every 64 taps of the fir filter. the default value of ssc 2-0 is 04h. ns 7-0 decay step number : this register defines the number of steps to be used for the decay of mu where each step has a period of ss taps (see ssc 2-0 ). the start of the exponential decay is defined as: filter length (512 or 1024) - [ decay step number (ns 7-0 ) x step size (ss) ] where ss = 4 x2 ssc 2-0 . for example, if ns 7-0 =4 and ssc 2-0 =4, then the exponential decay start value is 512 - [ns 7-0 x ss] = 512 - [4 x (4x2 4 )] = 256 taps for a filter length of 512 taps. fd
data sheet MT9122 19 power reset value n/a 76543210 rp 15 rp 14 rp 13 rp 12 rp 10 rp 9 rp 8 rp 11 echo canceller a, rin peak detect register 2 address = 0dh read echo canceller b, rin peak detect register 2 address = 2dh read power reset value n/a 76543210 rp 7 rp 6 rp 5 rp 4 rp 2 rp 1 rp 0 rp 3 echo canceller a, rin peak detect register 1 address = 0ch read echo canceller b, rin peak detect register 1 address = 2ch read these peak detector registers allow the user to monitor the receive in signal (rin) peak signal level. the information is in 16 -bit 2?s complement linear coded format presented in two 8 bit registers for each echo canceller. the high byte is in register 2 and the low byte is in register 1. rp rp power reset value n/a 76543210 sp 15 sp 14 sp 13 sp 12 sp 10 sp 9 sp 8 sp 11 echo canceller a, sin peak detect register 2 address = 0fh read echo canceller b, sin peak detect register 2 address = 2fh read power reset value n/a 76543210 sp 7 sp 6 sp 5 sp 4 sp 2 sp 1 sp 0 sp 3 echo canceller a, sin peak detect register 1 address = 0eh read echo canceller b, sin peak detect register 1 address = 2eh read these peak detector registers allow the user to monitor the send in signal (sin) peak signal level. the information is in 16-bi t 2?s complement linear coded format presented in two 8 bit registers for each echo canceller. the high byte is in register 2 and the low byte is in register 1. sp sp power reset value n/a 76543210 ep 15 ep 14 ep 13 ep 12 ep 10 ep 9 ep 8 ep 11 echo canceller a, error peak detect register 2 address = 11h read echo canceller b, error peak detect register 2 address = 31h read power reset value n/a 76543210 ep 7 ep 6 ep 5 ep 4 ep 2 ep 1 ep 0 ep 3 echo canceller a, error peak detect register 1 address = 10h read echo canceller b, error peak detect register 1 address = 30h read these peak detector registers allow the user to monitor the error signal peak level. the information is in 16-bit 2?s complemen t linear coded format presented in two 8 bit registers for each echo canceller. the high byte is in register 2 and the low byte i s in register 1. ep ep
20 MT9122 data sheet power reset value 48h 76543210 dtdt 15 dtdt 14 dtdt 13 dtdt 12 dtdt 10 dtdt 9 dtdt 8 dtdt 11 echo canceller a, double-talk detection threshold register 2 address = 15h write/read verify echo canceller b, double-talk detection threshold register 2 address = 35h write/read verify power reset value 00h 76543210 dtdt 7 dtdt 6 dtdt 5 dtdt 4 dtdt 2 dtdt 1 dtdt 0 dtdt 3 echo canceller a, double-talk detection threshold register 1 address = 14h write/read verify echo canceller b, double-talk detection threshold register 1 address = 34h write/read verify this register allows the user to program the level of double-talk detection threshold (dtdt). the 16 bit 2?s complement linear value defaults to 4800h= 0.5625 or -5db. the maximum value is 7fffh = 0.9999 or 0 db. the high byte is in register 2 and the low byte is in register 1. dtdt dtdt power reset value 08h 76543210 nlp 15 nlp 14 nlp 13 nlp 12 nlp 10 nlp 9 nlp 8 nlp 11 echo canceller a, non-linear processor threshold register 2 address = 19h write/read verify echo canceller b, non-linear processor threshold register 2 address = 39h write/read verify power reset value 00h 76543210 nlp 7 nlp 6 nlp 5 nlp 4 nlp 2 nlp 1 nlp 0 nlp 3 echo canceller a, non-linear processor threshold register 1 address = 18h write/read verify echo canceller b, non-linear processor threshold register 1 address = 38h write/read verify this register allows the user to program the level of the non-linear processor threshold (nlpthr). the 16 bit 2?s complement linear value defaults to 0800h = 0.0625 or -24.1db. the maximum value is 7fffh = 0.9999 or 0 db. the high byte is in register 2 and the low byte is in register 1. nlpthr nlpthr power reset value 40h 76543210 mu 15 mu 14 mu 13 mu 12 mu 10 mu 9 mu 8 mu 11 echo canceller a, adaptation step size (mu) register 2 address = 1bh write/read verify echo canceller b, adaptation step size (mu) register 2 address = 3bh write/read verify power reset value 00h 76543210 mu 7 mu 6 mu 5 mu 4 mu 2 mu 1 mu 0 mu 3 echo canceller a, adaptation step size (mu) register 1 address = 1ah write/read verify echo canceller b, adaptation step size (mu) register 1 address = 3ah write/read verify this register allows the user to program the level of mu. mu is a 16 bit 2?s complement value which defaults to 4000h = 1.0 the high byte is in register 2 and the low byte is in register 1. mu mu
data sheet MT9122 21 applications figure 12 - (basic rate isdn) wireless application diagram figure 13 - (analog trunk) wireless application diagram f0b dsto dsti t r c4o f0i mclk en1 en2 adpcmo adpcmi din dout stb1 sin rout bclk c20 bclk sout rin dsti dsto ena enb MT9122 mt9125 adpcm dual rf section mt8910 2b1q mt8972 bi-phase mt8931 s-int echo paths MT9122 is in ssi mode f0i din dout clockin t r mt8941 pll f0 t r mt9160 5v codec f0i mclk en1 en2 adpcmo adpcmi din dout stb1 c20 bclk dsti dsto mt9125 adpcm dual rf section c4 f0i din dout clockin mt9160 5v codec MT9122 is in ssi mode sin rout bclk sout rin ena enb MT9122 echo path echo path
22 MT9122 data sheet figure 14 - (analog trunk) wireless application diagram figure 15 - (basic rate isdn) wired telephone application diagram f0i din dout clockin t r f0 t r mt9160 5v codec f0i mclk en1 adpcmo adpcmi din dout stb1 c20 bclk dsti dsto mt9125 adpcm dual rf section echo path echo path c4 f0i din dout clockin mt9160 5v codec MT9122 connected in st-bus mode 1 sin rout sout rin MT9122 mt8941 pll f0i c4i f0b dsto dsti t r c4o f0i mclk sin sout rout rin dsti dsto MT9122 mt909x digital phone mt8910 2b1q mt8972 bi-phase mt8931 s-int echo path f0i c4i MT9122 in st-bus mode 1 using d&c channel bypass back-to-back configuration handset
data sheet MT9122 23 * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. * dc electrical characteristics are over recommended temperature and supply voltage. absolute maximum ratings* parameter symbol min max units 1 supply voltage v dd -v ss -0.3 7.0 v 2 voltage on any digital pin v i/o v ss -0.3 v dd + 0.3 v 3 continuous current on any digital pin i i/o 20 ma 4 storage temperature t st -65 150 c 5 package power dissipation p d 500 mw recommended operating conditions - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ ? max units test conditions 1 supply voltage v dd 4.5 5.0 5.5 v 2 ttl input high voltage 2.4 v dd v 400mv noise margin 3 ttl input low voltage v ss 0.4 v 400mv noise margin 4 cmos input high voltage 4.5 v dd v 5 cmos input low voltage v ss 0.5 v 6 operating temperature t a -40 +85 c dc electrical characteristics* - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ ? max units conditions/notes 1 supply current i cc i dd 70 100 a ma pwrdn = 0 pwrdn = 1, clocks active 2 input high voltage (ttl) v ih 2.0 v all except mclk,sin,rin 3 input low voltage (ttl) v il 0.8 v all except mclk,sin,rin 4 input high voltage (cmos) v ihc 3.5 v mclk,sin,rin 5 input low voltage (cmos) v ilc 1.5 v mclk,sin,rin 6 input leakage current i ih /i il 0.1 10 av in =v ss to v dd 7 high level output voltage v oh 0.9 v dd vi oh =2.5ma 8 low level output voltage v ol 0.1v dd vi ol =5.0ma 9 high impedance leakage i oz 110 av in =v ss to v dd 10 output capacitance c o 10 pf 11 input capacitance c i 8pf 12 pwrdn positive threshold voltage hysteresis negative threshold voltage v+ v h v- 3.75 1.0 1.25 v v v
24 MT9122 data sheet ? timing is over recommended temperature and power supply voltages. ac electrical characteristics ? - serial data interfaces (see figures 17 and 18) voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min max units test notes 1 mclk clock high t mch 20 ns 2 mclk clock low t mcl 20 ns 3 mclk frequency dual channel single channel f dclk f sclk 19.15 9.58 20.5 mhz mhz 4 bclk/c4i clock high t bch, t c4h 90 ns 5 bclk/c4i clock low t bll, t c4l 90 ns 6 bclk/c4i period t bcp 240 7900 ns 7 ssi enable strobe to data delay (first bit) t sd 80 ns c l =150pf 8 ssi data output delay (excluding first bit) t dd 80 ns c l =150pf 9 ssi output active to high impedance t ahz 80 ns c l =150pf 10 ssi enable strobe signal setup t sss 10 t bcp -15 ns 11 ssi enable strobe signal hold t ssh 15 t bcp -10 ns 12 ssi data input setup t dis 10 ns 13 ssi data input hold t dih 15 ns 14 f0i setup t f0is 20 150 ns 15 f0i hold t f0ih 20 150 ns 16 st-bus data output delay t dsd 80 ns c l =150pf 17 st-bus output active to high impedance t ashz 80 ns c l =150pf 18 st-bus data input hold time t dsh 20 ns 19 st-bus data input setup time t dss 20 ns 20 f0od delay t dfd 80 ns c l =150pf 21 f0od pulse width low t dfw 200 ns c l =150pf
data sheet MT9122 25 ? timing is over recommended temperature range and recommended power supply voltages. table 8 - reference level definition for timing measurements figure 16 master clock - mclk notes: 1. cmos output 2. ttl input compatible 3. cmos input (see table 8 for symbol definitions) ac electrical characteristics ? - microport timing (see figure 17) characteristics sym min max units test notes 1 input data setup t ids 100 ns 2 input data hold t idh 30 ns 3 output data delay t odd 100 ns c l =150pf 4 serial clock period t scp 500 ns 5 sclk pulse width high t sch 250 ns 6 sclk pulse width low t scl 250 ns 7cs setup-intel t cssi 200 ns 8cs setup-motorola t cssm 100 ns 9cs hold t csh 100 ns 10 cs to output high impedance t ohz 100 ns c l =150pf characteristic symbol ttl pin cmos pin units ttl reference level v tt 1.5 - v cmos reference level v ct -0.5*v dd v input high level v h 2.4 0.9*v dd v input low level v l 0.4 0.1*v dd v rise/fall high measurement point v hm 2.0 0.7*v dd v rise/fall low measurement point v hl 0.8 0.3*v dd v mclk (3) v h v l v ct t mch t mcl
26 MT9122 data sheet figure 17 - ssi data port timing notes: 1. cmos output 2. ttl input compatible 3. cmos input (see table 8 for symbol definitions) figure 18 - st-bus data port timing notes: 1. cmos output 2. ttl input compatible 3. cmos input (see table 8 for symbol definitions) sout/rout (1) v ct bclk (2) v h v l v tt ena1/ena2 (2) v h v l v tt rin/sin (3) v h v l v ct t sd t sss t dd t ahz t ssh t dis t dih t bcp t bch t bcl bit 0 bit 1 bit 0 bit 1 or enb1/enb2 (2) sout/rout (1) v ct c4i (2) v h v l v tt f0i (2) v h v l v tt rin/sin (3) v h v l v ct f0od (1) v ct t f0is t f0ih t dss t dsh t dsd t ashz t dfd t dfw t c4h t c4l bit 0 bit 1 bit 0 bit 1
data sheet MT9122 27 figure 19 - intel serial microport timing notes: 1. cmos output 2. ttl input compatible 3. cmos input (see table 8 for symbol definitions) figure 20 - motorola serial microport timing notes: 1. cmos output 2. ttl input compatible 3. cmos input (see table 8 for symbol definitions) data1 (1, 2) v tt ,v ct sclk (2) v h v l v tt cs ( 2) v h v l v tt t ids t idh t odd t ohz t cssi t csh t scl t sch t scp data input data output data2 (2) v h v l v tt sclk (2) v h v l v tt cs (2) v h v l v tt data1 (1) v ct t ids t idh t odd t cssm t csh t ohz t sch t scl t scp (input) (output)
28 MT9122 data sheet notes:

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